EE Test Engineer Cheat Sheet

Every test boils down to three questions: what am I measuring, why does it matter, and which tool + setup gives a trustworthy number. Each section below answers those for one area, and links to the interactive plots and instruments where you can try it.

The bench: which tool does what

InstrumentWhat it showsTypical uses
Oscilloscope + probesVoltage vs. timeEdges, ripple, transients, step response, eye diagramsTry it
DMM (multimeter)Accurate DC/AC volts, amps, ohmsDC levels, regulation, quiescent current, continuityTry it
Spectrum analyzerPower vs. frequencyHarmonics, spurs, noise floor, EMI pre-scanTry it
VNA (vector network analyzer)S-parameters vs. frequencyCables, filters, connectors, impedance matchingS11 plot
BERT / pattern generatorBit errors over millions of bitsBER, jitter tolerance, link marginBER plot
Programmable power supplyControlled input voltageLine regulation, brown-out, power sequencingTry it
Electronic loadControlled current drawLoad regulation, load-step transient responseTry it
Power analyzerTrue input and output powerEfficiency, power factor, standby power
Current probe (Hall / clamp)Current vs. time on a scopeInrush, ripple current, switching current
Function generator / AWGStimulus signalsFrequency response, step inputs, test patternsTry it
TDR (scope or VNA mode)Impedance vs. distanceFinding discontinuities on traces and cables
Thermal camera / thermocoupleTemperatureHot spots, derating, thermal validation

Inside a scope probe

The probe is part of the circuit you're measuring. Understand it and half of all "weird scope readings" explain themselves.

Digital and high-speed signals

The question here is always: does each bit arrive on time and at a clear level?

MeasurementWhat it meansHow to measureTip
Rise / fall timeTime for an edge to go 10% → 90% (or 20–80%). Too slow = timing errors; too fast = ringing and EMI.Scope auto-measureScope + probe bandwidth should be 3–5× faster than the edge. Scope rise time ≈ 0.35 / BW.
Overshoot / ringingEdge shoots past its final level and oscillates. Usually impedance mismatch or stray inductance.Scope, as % of amplitudeUse the short ground spring, not the long ground lead (the lead itself rings).
Timing: delay, skew, setup/holdWhen edges arrive relative to each other or to the clock.Scope, 2+ channels, measure 50% to 50%Deskew probes first; cables add about 5 ns per metre.
JitterEdges arriving early or late vs. the ideal time. Random jitter (RJ) is unbounded; deterministic (DJ) is bounded (data-dependent, crosstalk, periodic).Scope jitter analysis (TIE histogram); phase-noise analyzer for clocksTotal jitter is quoted at a BER: TJ ≈ DJ + 14 × RJ(rms) at 10⁻¹².
ISI (inter-symbol interference)Earlier bits smear into the current bit because the channel loses high frequencies (trace/cable loss) and reflects. Shows up as data-dependent jitter and a closing eye; worst for a lone bit after a long run of 1s or 0s.Eye diagram and DDJ at the receiver with a long pattern (PRBS31); channel loss as VNA S21 at the Nyquist frequency (bit rate ÷ 2)If the PRBS31 eye is much worse than PRBS7, ISI is the culprit. The fix is emphasis / equalization (last row).
Eye diagramAll bits overlaid. Open eye = healthy link. Height = noise margin, width = timing margin.Scope eye mode with clock recovery, checked against a maskAny mask hit = fail. Measure at the receiver end of the channel.
BER (bit error rate)Errors ÷ bits sent. Typical spec: 10⁻¹².BERT sending a PRBS pattern (PRBS7, PRBS31)To claim 10⁻¹² at 95% confidence with zero errors you need ~3 × 10¹² bits (about 5 min at 10 Gb/s).
Pre-/de-emphasis, EQThe transmitter boosts transitions to pre-compensate cable loss at high frequency; the receiver's CTLE/DFE equalizer does the same at the far end.Sweep emphasis/EQ settings, compare eye opening or BERMore is not better: too much emphasis closes the eye again. Pick the setting with best margin.

Power electronics

The question: is the output clean, stable and efficient across every input voltage and every load?

MeasurementWhat it meansHow to measureTip
Ripple and noiseThe AC wiggle riding on the DC output, mostly at the switching frequency, plus spikes. Spec'd in mV peak-to-peak.Scope, AC-coupled, 20 MHz bandwidth limit, probe right at the output capacitorA long ground lead picks up switching noise and shows fake ripple: use a ground spring or tip-and-barrel. Measure at full load.
Line regulationHow much Vout moves when Vin moves. % = ΔVout ÷ Vout(nominal) × 100, over the full Vin range.Programmable supply sweeps Vin min → max at fixed load; DMM on VoutSense voltage at the board (4-wire / Kelvin) so cable drop doesn't count.
Load regulationHow much Vout moves from no load to full load. % = (V(no load) − V(full load)) ÷ V(nominal) × 100.Electronic load steps through load points; DMM on VoutSame 4-wire rule. Let it warm up before reading.
Load transient responseDip or overshoot and recovery time when the load changes fast (e.g. 10% → 90%).E-load in dynamic mode (set the slew rate), scope on Vout, trigger on the load currentReport peak deviation (mV) and time to get back inside the band. Ringing hints at a weak control loop.
Efficiencyη = Pout ÷ Pin × 100%. The rest turns into heat.Power analyzer, or 4 DMMs: Vin, Iin, Vout, IoutPlot it from 10% to 100% load; light load is often worst. Wait for thermal steady state.
Inrush currentThe current spike at turn-on while input capacitors charge. Can trip breakers, blow fuses, weld relay contacts.Current probe on the input, scope in single-shot mode, trigger on rising currentFully discharge caps between tries. Worst case: max Vin, or AC switched on at the voltage peak.
Quiescent / standby currentCurrent drawn with no load. Decides battery life.DMM in series on the µA rangeWatch the meter's burden voltage on low ranges.
Protections and start-upDoes it shut down safely on short circuit, overvoltage, overtemperature? Do rails power up in the right order?E-load short mode; multi-channel scope on all railsClassic interview topic: OCP, OVP, OTP, UVLO, soft-start, sequencing.

Analog and RF

The question: how much of what comes out is the real signal, and how much is noise, distortion or loss?

MeasurementWhat it meansHow to measureTip
SNR (signal-to-noise ratio)Signal power ÷ noise power, in dB. Higher = cleaner.Spectrum analyzer, or FFT of a scope/ADC capture: signal peak vs. total noise in the bandAlways state the bandwidth: more bandwidth = more noise. Ideal ADC: SNR = 6.02 × bits + 1.76 dB.
Noise floorThe lowest level the system can see: the "grass" at the bottom of the spectrum.Spectrum analyzer with the input terminated in 50 ΩNarrower RBW lowers the displayed floor (10× narrower = −10 dB). Physics limit: −174 dBm/Hz at room temperature.
THD, SINAD, ENOBTHD = harmonics vs. the fundamental. SINAD = signal vs. noise + distortion. ENOB = (SINAD − 1.76) ÷ 6.02.Very clean sine in (low-distortion generator + filter), FFT the outputUse a window (Blackman-Harris) or coherent sampling, or the FFT smears and lies.
Bandwidth / frequency responseGain vs. frequency. Bandwidth = where gain drops 3 dB.Swept sine (generator + scope), Bode analyzer, or VNA S21Sweep log-spaced points; check phase too, not only gain.
Spectrum, spurs, EMIWhich frequencies are present: clocks, switching harmonics, interference.Spectrum analyzer; near-field probes to find the sourceIf a spur changes when you add input attenuation, the analyzer is overloaded, not the DUT.
S-parametersHow a device reflects and passes RF. S11 = input match, S21 = gain/loss through, S22 = output match, S12 = reverse isolation.VNA, calibrated (SOLT: short, open, load, thru) at the cable endsRecalibrate whenever cables, adapters or the frequency span change. S11 of −20 dB ≈ VSWR 1.22.

Control systems

The question: when the setpoint or load changes, does the loop get there fast, without overshooting too much, and stay there? Almost everything comes from one test: apply a step and record the output.

MeasurementWhat it meansHow to measureTip
OvershootHow far the output goes past its final value. % = (peak − final) ÷ final × 100.Step the setpoint (or the load); capture on scope or data logger; read the peakMore overshoot = less damping = closer to instability.
UndershootThe output dips below the final value after the overshoot (or first moves the wrong way).Same captureSeveral big swings back and forth = ringing = a lightly damped loop.
Rise time10% → 90% of the final value: how fast the loop reacts.Scope cursors on the step captureFaster usually costs overshoot: it's a trade-off.
Settling timeTime until the output enters the band (±2% or ±5%) and never leaves again.Same capture, measured to the last time it exits the bandRough estimate: 4 ÷ (ζωn) for the 2% band.
Steady-state errorGap between setpoint and where the output finally rests.Averaged DMM or logger reading after settlingIntegral action (the I in PID) drives it to zero.
Gain and phase marginHow far the loop is from oscillating. Common targets: phase margin ≥ 45°, gain margin ≥ 6–10 dB.Frequency-response (Bode) analyzer injecting a small signal across a 5–50 Ω resistor in the feedback pathThis is how power-supply loops are checked. ~45° PM gives roughly 20–25% overshoot; ~60° about 10%.

Bench tips that interviewers love

A good test engineer always asks: could my setup be causing what I see?

Quick formulas

FormulaWhen you need it
dB (power) = 10 log(P2 ÷ P1); dB (voltage) = 20 log(V2 ÷ V1)Everything in dB. 3 dB = 2× power, 6 dB = 2× voltage, 20 dB = 10× voltage.
0 dBm = 1 mW ≈ 0.224 Vrms into 50 Ω; dBµV = dBm + 107 (50 Ω)Reading a spectrum analyzer or EMI receiver
Vrms = Vpeak ÷ √2 (sine only)DMM AC readings
Scope rise time ≈ 0.35 ÷ bandwidthIs my scope fast enough?
Nyquist: f_max = sample rate ÷ 2Will my scope or ADC alias this signal?
SNR(ideal ADC) = 6.02 × N + 1.76 dBADC testing, ENOB
Thermal noise = √(4kTRB); −174 dBm/Hz at 290 KThe lowest noise floor possible
Γ = (ZL − Z0) ÷ (ZL + Z0); VSWR = (1 + |Γ|) ÷ (1 − |Γ|)Reflections, impedance matching
Bits to test ≈ 3 ÷ target BERBER at 95% confidence with zero errors
η = Pout ÷ Pin; Ploss = Pin − PoutEfficiency and heat
Meter error ≈ Rsource ÷ (Rsource + Rin)Loading by a DMM or probe
Uncertainty (independent errors) = √(e1² + e2² + …)Uncertainty budgets

Adapted from the "EE Test Engineer Cheat Sheet" (Seba, 3 Nov 2026), with links into this tool.